The present invention relates to a highly integrated semiconductor device and a method for manufacturing the same. More particularly, it relates to a Metal Oxide Semiconductor (MOS) transistor having a vertical structure which enables increased integration, and a method for manufacturing the same.
It is important to place a maximum number of devices in a minimum cell area to increase integration. In particular, the increased integration of devices is important to increase the density of a semiconductor memory cell device, especially a dynamic random access memory (DRAM).
Conventional devices traditionally form a transistor in a lateral direction on a semiconductor substrate. However, the formation of source and drain regions and the gate of each transistor in such planar devices proves to be a major factor impeding a further reduction of the size of memory cells of such semiconductor memory devices. The continued reduction in the lateral size of planar-formed high capacity memory devices, such as 256 Mbit and higher, causes a deterioration in the electrical characteristics of the memory cells. Thus, it is substantially impossible to realize a semiconductor memory device of a continued higher capacity using the conventional planar layout.
In an attempt to overcome the disadvantages of the conventional planar layout, various memory cell structures have been proposed wherein a transistor and capacitor are formed on a semiconductor substrate in a vertical direction are proposed.
K. Sunouchi et al. suggest a Surrounding Gate Transistor (SGT) cell wherein all devices for the unit memory cell are formed in one silicon pillar isolated by a matrix-like trench. See K. Sunouchi et al., "A Surrounding Gate Transistor (SGT) Cell for 64/256 Mbit DRAMs", IEDM 1989. However, in this proposed SGT cell, the process of forming the silicon pillar and the capacitor are complex and the isolation characteristics are poor. Also, there is a large possibility that a short between a capacitor plate-node and a gate electrode will occur during the process forming the gate electrode.
Digh Hisamoto et al. suggest a Fully Depleted Lean-channel Transistor (DELTA) structure wherein a gate electrode having a silicon on insulator (SOI) structure is vertically formed. See Digh Hisamoto et al., "A Fully Depleted Lean-channel Transistor (DELTA)", IEDM 1989. The DELTA structure has effective channel controllability since the channel is formed on a vertical surface. However, an increase in the integration of such devices is limited since source and drain regions are laterally formed with respect to the gate.
Toshiyuki Nishihara et al. suggest a SOI structure cell wherein a capacitor is completely buried under a silicon layer, to maximize a memory cell area. See Toshiyuki Nishihara et al., "A Buried Capacitor DRAM Cell with Bonded SOI for 256 M and 1 Gbit DRAMs", IEDM 1992. However, in this SOI structure cell, it is difficult to control a remaining silicon layer thickness during the process of polishing a silicon substrate for forming the SOI structure. Moreover, this structure requires an additional bitline contact hole area for connecting a drain region of a transistor with the bitline.